3.6.21 Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
Model type: nmos or pmos
Syntax:
M name (nodeDnodeGnodeSnodeB) model_name
+ param[=value]…
nmos sets the model to be an nchannel MOSFET model and pmos makes it a pchannel MOSFET model. When specifying a MOSFET instance, all four nodes must be supplied in the following order: drain, gate, source, and bulk. See Fig. 3.25 for the symbol of a MOSFET.
3.6.22 Legacy MOSFET Models (Levels 1–6)
3.6.22.1 Level 1 MOSFET Model
The level 1 model is also known as the Shichman–Hodges model [45]. Tables 3.52–3.55 list the level 1 MOSFET parameters, properties calculated by the simulator, and noise contributions.
Effective values of instance parameters l, w, pd, and ps are obtained by scaling the values from the netlist with simulator parameter SCALE. ad and as are scaled with SCALE^{2}.
Fig. 3.25
The symbol and the terminals of an nchannel (left) and a pchannel (right) MOSFET
Table 3.52
MOSFET level 1 instance parameters
Name

Unit

Default

Description


l

SCALE m

DEFL

Channel length

w

SCALE m

DEFW

Channel width

ad

SCALE^{2} m^{2}

DEFAD

Drain area

as

SCALE^{2} m^{2}

DEFAS

Source area

pd

SCALE m

DEFPD

Drain perimeter

ps

SCALE m

DEFPS

Source perimeter

nrd

–

DEFNRD

Drain squares (quotient of drain length and width)

nrs

–

DEFNRS

Source squares (quotient of source length and width)

m

–

1

Number of parallel instances

temp

^{∘}C

TEMP

Device temperature

off

–

Not set

Flag that turns off the device in the first NR iteration of DC analysis

icvds

V

0

Initial D–S voltage (internal MOS instance)

icvgs

V

0

Initial G–S voltage (internal MOS instance)

icvbs

V

0

Initial B–S voltage (internal MOS instance)

Table 3.53
MOSFET level 1 model parameters
Name

Unit

Default

Description


vto

V

0

Threshold voltage

kp

A∕V^{2}

2 ⋅10^{ − 5}

Transconductance parameter

gamma

V^{1∕2}

0

Bulk threshold parameter

phi

V

0. 6

Surface potential

lambda

1∕V

0

Channel length modulation

rd

Ω

0

Drain resistance

rs

Ω

0

Source resistance

cbd

F

0

B–D junction capacitance

cbs

F

0

B–S junction capacitance

is

A

10^{ − 14}

Bulk junction saturation current

n

–

1

Emission coefficient

pb

V

0. 8

Bulk junction potential

cgso

F∕m

G–S overlap capacitance


cgdo

F∕m

G–D overlap capacitance


cgbo

F∕m

G–B overlap capacitance


rsh

Ω∕□

0

Sheet resistance

cj

F∕m^{2}

0

Bottom junction capacitance per area

mj

–

0. 5

Bottom grading coefficient

cjsw

F∕m

0

Side junction capacitance per area

mjsw

–

0. 5

Side grading coefficient

js

A∕m^{2}

0

Bulk junction saturation current density

tox

m

Oxide thickness


ld

m

0

Lateral diffusion

wd

m

0

Lateral diffusion into channel width from bulk

xl

m

0

Length bias accounts for masking and etching effects

xw

m

0

Width bias accounts for masking and etching effects

delvto

V

0

Zerobias threshold voltage shift

uo

cm^{2}∕Vs

600

Surface mobility

bex

–

− 1. 5

Low field mobility temperature exponent

fc

–

0. 5

Forward bias junction fit parameter

nsub

1∕cm^{3}

Substrate doping


tpg

–

1

Gate type (0.. Al gate, 1.. same as sourcedrain diffusion, − 1.. opposite to sourcedrain diffusion)

nss

1∕cm^{2}

0

Surface state density

tnom

^{∘}C

TNOM

Parameter measurement temperature

kf

–

0

Flicker noise coefficient

af

–

1

Flicker noise exponent

Table 3.54
MOSFET level 1 properties calculated by the simulator
Name

Unit

Description


id

A

Drain current

is

A

Source current

ig

A

Gate current

ib

A

Bulk current

ibd

A

B–D junction current

ibs

A

B–S junction current

vgs

V

G–S voltage

vds

V

D–S voltage

vbs

V

B–S voltage

vbd

V

B–D voltage

gm

A∕V

Transconductance

gds

A∕V

D–S conductance

gmb

A∕V

B–S transconductance

gbd

A∕V

B–D conductance

gbs

A∕V

B–S conductance

cbd

F

B–D capacitance

cbs

F

B–S capacitance

cgs

F

G–S capacitance

cgd

F

G–D capacitance

cgb

F

G–B capacitance

cqgs

F

Capacitance due to G–S charge storage

cqgd

F

Capacitance due to G–D charge storage

cqgb

F

Capacitance due to G–B charge storage

cqbd

F

Capacitance due to B–D charge storage

cqbs

F

Capacitance due to B–S charge storage

cbd0

F

Zerobias B–D junction capacitance

cbdsw0

F

Zerobias B–D sidewall junction capacitance

cbs0

F

Zerobias B–S junction capacitance

cbssw0

F

Zerobias B–S sidewall junction capacitance

qgs

As

G–S charge storage

qgd

As

G–D charge storage

qgb

As

G–B charge storage

qbd

As

B–D charge storage

qbs

As

B–S charge storage

p

W

Power dissipation

All these quantities are evaluated in the transient analysis. In DC analysis capacitances and charges are not evaluated.
Level 1 MOSFETs have up to two internal nodes. Nodes M name#drain and M name#source are created if the drain and source resistances are greater than zero, respectively.
Table 3.55
MOSFET level 1 noise contributions
Postfix

Description


_rd

Drain series resistance thermal noise

_rs

Source series resistance thermal noise

_id

Drain current shot noise

_1overf

Flicker noise

No postfix

Total MOSFET noise contribution

Example:
* A CMOS inverter circuit m1 (out in vdd vdd) pm w=10u l=2u m2 (out in vss vss) nm w=5u l=2u .model nm nmos (level=1 kp=4e5) .model pm pmos (level=1 kp=2e5)
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