Automatic Analog Layout Generation

Design Environment: Mentor Graphics
Language: Perl
OS: Unix

An algorithm is developed for designing an automatic Op-amp layout generation by using scripting language. The layout of the two-stage Op-amp will automatically draw out in the Mentor Graphics IC station by inserting the essential data. The main challenges are design a common-centroid layout template, and how to route each transistor automatically without violating the DRC (Design Rule Check).

The algorithm invokes DRC file, using circuit netlist information to generate circuit layout automatically with a common-centroid layout template.

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