Level 5 MOSFET Model

BSIM2 is an improved variant of the BSIM1 model [13]. It has the same set of instance parameters as the level 1 MOSFET model.
All BSIM1 model parameters are supported except eta, leta, weta, x2e, lx2e, wx2e, x3e, lx3e, wx3e, muz, x2mz, lx2mz, wx2mz, mus, lmus, wmus, x2ms, lx2ms, wx2ms, x3ms, lx3ms, wx3ms, u0, lu0, wu0, x2u0, lx2u0, wx2u0, u1, lu1, wu1, x2u1, lx2u1, wx2u1, x3u1, lx3u1, and wx3u1. BSIM2 models also support some additional parameters. See Table 3.60.
Table 3.59

BSIM1 MOSFET (level 4) model parameters
Name
Unit
Description
vfb
V
Flatband voltage
lvfb
V ⋅μm
Length dependence of vfb
wvfb
V ⋅μm
Width dependence of vfb
phi
V
Strong inversion surface potential
lphi
V ⋅μm
Length dependence of phi
wphi
V ⋅μm
Width dependence of phi
k1
V1∕2
Bulk effect coefficient 1
lk1
V1∕2 ⋅μm
Length dependence of k1
wk1
V1∕2 ⋅μm
Width dependence of k1
k2
Bulk effect coefficient 2
lk2
μm
Length dependence of k2
wk2
μm
Width dependence of k2
eta
V ds dependence of threshold voltage
leta
μm
Length dependence of eta
weta
μm
Width dependence of eta
x2e
1∕V
V bs dependence of eta
lx2e
μm∕V
Length dependence of x2e
wx2e
μm∕V
Width dependence of x2e
x3e
1∕V
V ds dependence of eta
lx3e
μm∕V
Length dependence of x3e
wx3e
μm∕V
Width dependence of x3e
dl
μm
Channel length reduction
dw
μm
Channel width reduction
muz
cm2∕Vs
Zero field mobility at V ds = 0, V gs = V th
x2mz
cm2∕V2s
V bs dependence of muz
lx2mz
μm ⋅ cm2∕V2s
Length dependence of x2mz
wx2mz
μm ⋅ cm2∕V2s
Width dependence of x2mz
mus
cm2∕Vs
Mobility at V ds = V dd , V gs = V th , channel length modulation
lmus
μm ⋅ cm2∕Vs
Length dependence of mus
wmus
μm ⋅ cm2∕Vs
Width dependence of mus
x2ms
cm2∕V2s
V bs dependence of mus
lx2ms
μm ⋅ cm2∕V2s
Length dependence of x2ms
wx2ms
μm ⋅ cm2∕V2s
Width dependence of x2ms
x3ms
cm2∕V2s
V ds dependence of mus
lx3ms
μm ⋅ cm2∕V2s
Length dependence of x3ms
wx3ms
μm ⋅ cm2∕V2s
Width dependence of x3ms
u0
1∕V
V gs dependence of mobility
lu0
μm∕V
Length dependence of u0
wu0
μm∕V
Width dependence of u0
x2u0
1∕V2
V bs dependence of u0
lx2u0
μm∕V2
Length dependence of x2u0
wx2u0
μm∕V2
Width dependence of x2u0
u1
μm∕V
V ds dependence of mobility, velocity saturation
lu1
μm2∕V
Length dependence of u1
wu1
μm2∕V
Width dependence of u1
x2u1
μm∕V2
V bs dependence of u1
lx2u1
μm2∕V2
Length dependence of x2u1
wx2u1
μm2∕V2
Width dependence of x2u1
x3u1
μm∕V2
V ds dependence of u1
lx3u1
μm2∕V2
Length dependence of x3u1
wx3u1
μm2∕V2
Width dependence of x3u1
n0
Subthreshold slope
ln0
Length dependence of n0
wn0
Width dependence of n0
nb
V bs dependence of subthreshold slope
lnb
Length dependence of nb
wnb
Width dependence of nb
nd
V ds dependence of subthreshold slope
lnd
Length dependence of nd
wnd
Width dependence of nd
tox
μm
Gate oxide thickness
temp
C
Temperature at which parameters were measured
vdd
V
Supply voltage to specify mus
cgso
F∕m
G–S overlap capacitance per unit channel width
cgdo
F∕m
G–D overlap capacitance per unit channel width
cgbo
F∕m
G–B overlap capacitance per unit channel length
xpart
Flag for channel charge partitioning
rsh
Ω∕□
Source drain diffusion sheet resistance
js
A∕m2
Source drain junction saturation current per unit area
pb
V
Source drain junction built-in potential
mj
Source drain bottom junction capacitance grading coefficient
pbsw
V
Source drain side junction capacitance built-in potential
mjsw
Source drain side junction capacitance grading coefficient
cj
F∕m2
Source drain bottom junction capacitance per unit area
cjsw
F∕m
Source drain side junction capacitance per unit area
wdf
m
Default width of source drain diffusion
dell
m
Length reduction of source drain diffusion
Table 3.60

Additional BSIM2 MOSFET (level 5) model parameters
Name
Unit
Description
eta0
V ds dependence of threshold voltage at V dd = 0
leta0
μm
Length dependence of eta0
weta0
μm
Width dependence of eta0
etab
1∕V
V bs dependence of eta
letab
μm∕V
Length dependence of etab
wetab
μm∕V
Width dependence of etab
mu0
cm2∕Vs
Low-field mobility, at V ds = 0, V gs = V th
mu0b
cm2∕V2s
V bs dependence of low-field mobility
lmu0b
μm ⋅ cm2∕V2s
Length dependence of mu0b
wmu0b
μm ⋅ cm2∕V2s
Width dependence of mu0b
mus0
cm2∕Vs
Mobility at V ds = V dd , V gs = V th
lmus0
μm ⋅ cm2∕Vs
Length dependence of mus0
wmus0
μm ⋅ cm2∕Vs
Width dependence of mus0
musb
cm2∕V2s
V bs dependence of mus0
lmusb
μm ⋅ cm2∕V2s
Length dependence of musb
wmusb
μm ⋅ cm2∕V2s
Width dependence of musb
mu20
V ds dependence of mu in tanh term
lmu20
μm
Length dependence of mu20
wmu20
μm
Width dependence of mu20
mu2b
1∕V
V bs dependence of mu20
lmu2b
μm∕V
Length dependence of mu2b
wmu2b
μm∕V
Width dependence of mu2b
mu2g
1∕V
V gs dependence of mu20
lmu2g
μm∕V
Length dependence of mu2g
wmu2g
μm∕V
Width dependence of mu2g
mu30
cm2∕V2s
V ds dependence of mu in linear term
lmu30
μm ⋅ cm2∕V2s
Length dependence of mu30
wmu30
μm ⋅ cm2∕V2s
Width dependence of mu30
mu3b
cm2∕V3s
V bs dependence of mu3
lmu3b
μm ⋅ cm2∕V3s
Length dependence of mu3b
wmu3b
μm ⋅ cm2∕V3s
Width dependence of mu3b
mu3g
cm2∕V3s
V gs dependence of mu3
lmu3g
μm ⋅ cm2∕V3s
Length dependence of mu3g
wmu3g
μm ⋅ cm2∕V3s
Width dependence of mu3g
mu40
cm2∕V3s
V ds dependence of mu in linear term
lmu40
μm ⋅ cm2∕V3s
Length dependence of mu40
wmu40
μm ⋅ cm2∕V3s
Width dependence of mu40
mu4b
cm2∕V4s
V bs dependence of mu40
lmu4b
μm ⋅ cm2∕V4s
Length dependence of mu4b
wmu4b
μm ⋅ cm2∕V4s
Width dependence of mu4b
mu4g
cm2∕V4s
V gs dependence of mu40
lmu4g
μm ⋅ cm2∕V4s
Length dependence of mu4g
wmu4g
μm ⋅ cm2∕V4s
Width dependence of mu4g
ua0
1∕V
Linear V gs dependence of mobility
lua0
μm∕V
Length dependence of ua0
wua0
μm∕V
Width dependence of ua0
uab
1∕V2
V bs dependence of ua0
luab
μm∕V2
Length dependence of uab
wuab
μm∕V2
Width dependence of uab
ub0
1∕V2
Quadratic V gs dependence of mobility
lub0
μm∕V2
Length dependence of ub0
wub0
μm∕V2
Width dependence of ub0
ubb
1∕V3
V bs dependence of ub0
lubb
μm∕V3
Length dependence of ubb
wubb
μm∕V3
Width dependence of ubb
u10
1∕V
V ds dependence of mobility
lu10
μm∕V
Length dependence of u10
wu10
μm∕V
Width dependence of u10
u1b
1∕V2
V bs dependence of u10
lu1b
μm∕V2
Length dependence of u1b
wu1b
μm∕V2
Width dependence of u1b
u1d
1∕V2
V ds dependence of u10
lu1d
μm∕V2
Length dependence of u1d
wu1d
μm∕V2
Width dependence of u1d
vof0
Threshold voltage offset at V ds = 0, V bs = 0
lvof0
μm
Length dependence of vof0
wvof0
μm
Width dependence of vof0
vofb
1∕V
V bs dependence of vof0
lvofb
μm∕V
Length dependence of vofb
wvofb
μm∕V
Width dependence of vofb
vofd
1∕V
V ds dependence of vof0
lvofd
μm∕V
Length dependence of vofd
wvofd
μm∕V
Width dependence of vofd
ai0
Impact ionization coefficient
lai0
μm
Length dependence of ai0
wai0
μm
Width dependence of ai0
aib
1∕V
V bs dependence of ai0
laib
μm∕V
Length dependence of aib
waib
μm∕V
Width dependence of aib
bi0
V
Impact ionization exponent
lbi0
μm ⋅ V
Length dependence of bi0
wbi0
μm ⋅ V
Width dependence of bi0
bib
V bs dependence of bi0
lbib
μm
Length dependence of bib
wbib
μm
Width dependence of bib
vghigh
V
Upper bound of the weak-strong inversion transition region
lvghigh
μm ⋅ V
Length dependence of vghigh
wvghigh
μm ⋅ V
Width dependence of vghigh
vglow
V
Lower bound of the weak-strong inversion transition region
lvglow
μm ⋅ V
Length dependence of vglow
wvglow
μm ⋅ V
Width dependence of vglow
vgg
V
Maximum V gs
vbb
V
Maximum V bs
BSIM2 instances have no instance properties calculated by the simulator. The set of internal nodes is the same as in level 1 MOSFETs. BSIM2 instances have no noise contributions.
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Level 4 MOSFET Model (BSIM1)

BSIM is short for Berkeley short-channel IGFET (insulated gate FET) model. This is the beginning of a long line of BSIM models used mostly in IC design.
The set of instance parameters is the same as in the level 1 model.
BSIM models are designed for use with a process characterization system. Therefore, model parameters have no default values. Omitting a parameter is considered to be an error. A more detailed description of the model parameters can be found in [44].
BSIM models have many parameters. See Table 3.59. These parameters are usually unimportant to an IC designer, as they are extracted at the foundry which supplies the models for the devices that are created by its manufacturing processes. IC designers focus mostly on choosing the device geometry and circuit layout.
BSIM1 instances have no instance properties calculated by the simulator. The set of internal nodes is the same as in level 1 MOSFETs. BSIM1 instances have no noise contributions.
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Level 3 MOSFET Model

This model is based on [12, 55]. The set of instance parameters is the same as in the level 2 MOSFET model. All level 2 model parameters except lambda, utra, uexp, ucrit, and neff are supported, and some additional parameters are available. See Table 3.58.
Table 3.58

Additional MOSFET level 3 model parameters
Name
Unit
Default
Description
eta
0
Static feedback factor for adjusting threshold
theta
1 ∕ V
0
Mobility degradation factor
kappa
1 ∕ V
0. 2
Saturation field factor
The set of values calculated by the simulator, noise contributions, and internal nodes are the same as in the level 2 model.
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Level 2 MOSFET Model

The level 2 MOSFET model is also known as the Grove–Frohman model [18].
The set of instance parameters is the same as in the level 1 model. All level 1 model parameters are supported along with some additional parameters. See Tables 3.56 and 3.57.

Table 3.56

Additional MOSFET level 2 model parameters
Name
Unit
Default
Description
utra
0
Transverse field coefficient
delta
0
Width effect on threshold
uexp
0
Critical field exponent for surface mobility degradation
ucrit
V∕cm
104
Critical field for mobility degradation
vmax
m∕s
0
Maximum drift velocity of carriers
xj
m
0
Junction depth
neff
1
Total channel charge coefficient
nfs
1∕cm2
0
Fast surface state density
The set of values calculated by the simulator is the same as in the level 1 model. Six additional quantities are calculated.

Table 3.57

Additional MOSFET level 2 properties calculated by the simulator
Name
Unit
Description
vth
V
Threshold voltage
vdsat
V
Saturation drain voltage
sourcevcrit
V
Critical source voltage
drainvcrit
V
Critical drain voltage
rs
Ω
Source resistance
rd
Ω
Drain resistance
The set of noise contributions and internal nodes is the same as in the level 1 model.
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Level 1 MOSFET Model

3.6.21 Metal Oxide Semiconductor Field Effect Transistor (MOSFET)

Model type: nmos or pmos
Syntax:
M name (nodeDnodeGnodeSnodeB) model_name
+ param[=value]…
nmos sets the model to be an n-channel MOSFET model and pmos makes it a p-channel MOSFET model. When specifying a MOSFET instance, all four nodes must be supplied in the following order: drain, gate, source, and bulk. See Fig. 3.25 for the symbol of a MOSFET.

3.6.22 Legacy MOSFET Models (Levels 1–6)

3.6.22.1 Level 1 MOSFET Model

The level 1 model is also known as the Shichman–Hodges model [45]. Tables 3.523.55 list the level 1 MOSFET parameters, properties calculated by the simulator, and noise contributions.
Effective values of instance parameters l, w, pd, and ps are obtained by scaling the values from the netlist with simulator parameter SCALE. ad and as are scaled with SCALE2.
/static-content/images/250/chp%253A10.1007%252F978-0-8176-4867-1_3/MediaObjects/978-0-8176-4867-1_3_Fig25_HTML.gif
Fig. 3.25

The symbol and the terminals of an n-channel (left) and a p-channel (right) MOSFET
Table 3.52

MOSFET level 1 instance parameters
Name
Unit
Default
Description
l
SCALE m
DEFL
Channel length
w
SCALE m
DEFW
Channel width
ad
SCALE2 m2
DEFAD
Drain area
as
SCALE2 m2
DEFAS
Source area
pd
SCALE m
DEFPD
Drain perimeter
ps
SCALE m
DEFPS
Source perimeter
nrd
DEFNRD
Drain squares (quotient of drain length and width)
nrs
DEFNRS
Source squares (quotient of source length and width)
m
1
Number of parallel instances
temp
C
TEMP
Device temperature
off
Not set
Flag that turns off the device in the first NR iteration of DC analysis
icvds
V
0
Initial D–S voltage (internal MOS instance)
icvgs
V
0
Initial G–S voltage (internal MOS instance)
icvbs
V
0
Initial B–S voltage (internal MOS instance)
Table 3.53

MOSFET level 1 model parameters
Name
Unit
Default
Description
vto
V
0
Threshold voltage
kp
A∕V2
2 ⋅10 − 5
Transconductance parameter
gamma
V1∕2
0
Bulk threshold parameter
phi
V
0. 6
Surface potential
lambda
1∕V
0
Channel length modulation
rd
Ω
0
Drain resistance
rs
Ω
0
Source resistance
cbd
F
0
B–D junction capacitance
cbs
F
0
B–S junction capacitance
is
A
10 − 14
Bulk junction saturation current
n
1
Emission coefficient
pb
V
0. 8
Bulk junction potential
cgso
F∕m
G–S overlap capacitance
cgdo
F∕m
G–D overlap capacitance
cgbo
F∕m
G–B overlap capacitance
rsh
Ω∕□
0
Sheet resistance
cj
F∕m2
0
Bottom junction capacitance per area
mj
0. 5
Bottom grading coefficient
cjsw
F∕m
0
Side junction capacitance per area
mjsw
0. 5
Side grading coefficient
js
A∕m2
0
Bulk junction saturation current density
tox
m
Oxide thickness
ld
m
0
Lateral diffusion
wd
m
0
Lateral diffusion into channel width from bulk
xl
m
0
Length bias accounts for masking and etching effects
xw
m
0
Width bias accounts for masking and etching effects
delvto
V
0
Zero-bias threshold voltage shift
uo
cm2∕Vs
600
Surface mobility
bex
− 1. 5
Low field mobility temperature exponent
fc
0. 5
Forward bias junction fit parameter
nsub
1∕cm3
Substrate doping
tpg
1
Gate type (0.. Al gate, 1.. same as source-drain diffusion, − 1.. opposite to source-drain diffusion)
nss
1∕cm2
0
Surface state density
tnom
C
TNOM
Parameter measurement temperature
kf
0
Flicker noise coefficient
af
1
Flicker noise exponent
Table 3.54

MOSFET level 1 properties calculated by the simulator
Name
Unit
Description
id
A
Drain current
is
A
Source current
ig
A
Gate current
ib
A
Bulk current
ibd
A
B–D junction current
ibs
A
B–S junction current
vgs
V
G–S voltage
vds
V
D–S voltage
vbs
V
B–S voltage
vbd
V
B–D voltage
gm
A∕V
Transconductance
gds
A∕V
D–S conductance
gmb
A∕V
B–S transconductance
gbd
A∕V
B–D conductance
gbs
A∕V
B–S conductance
cbd
F
B–D capacitance
cbs
F
B–S capacitance
cgs
F
G–S capacitance
cgd
F
G–D capacitance
cgb
F
G–B capacitance
cqgs
F
Capacitance due to G–S charge storage
cqgd
F
Capacitance due to G–D charge storage
cqgb
F
Capacitance due to G–B charge storage
cqbd
F
Capacitance due to B–D charge storage
cqbs
F
Capacitance due to B–S charge storage
cbd0
F
Zero-bias B–D junction capacitance
cbdsw0
F
Zero-bias B–D sidewall junction capacitance
cbs0
F
Zero-bias B–S junction capacitance
cbssw0
F
Zero-bias B–S sidewall junction capacitance
qgs
As
G–S charge storage
qgd
As
G–D charge storage
qgb
As
G–B charge storage
qbd
As
B–D charge storage
qbs
As
B–S charge storage
p
W
Power dissipation
All these quantities are evaluated in the transient analysis. In DC analysis capacitances and charges are not evaluated.
Level 1 MOSFETs have up to two internal nodes. Nodes M name#drain and M name#source are created if the drain and source resistances are greater than zero, respectively.
Table 3.55

MOSFET level 1 noise contributions
Postfix
Description
_rd
Drain series resistance thermal noise
_rs
Source series resistance thermal noise
_id
Drain current shot noise
_1overf
Flicker noise
No postfix
Total MOSFET noise contribution
Example:
* A CMOS inverter circuit m1 (out in vdd vdd) pm w=10u l=2u m2 (out in vss vss) nm w=5u l=2u .model nm nmos (level=1 kp=4e-5) .model pm pmos (level=1 kp=2e-5)
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Electronics circuit diagram/schematic drawing softwares list

electronic schematic drawing software

This article is an attempt to list out all available softwares for circuit drawing. I have taken into consideration many criteria before making this list. You know there are free softwares, paid softwares, sharewares and there will be variations in quality of softwares, user friendliness, complexities etc. I have tried to include as many software as possible. For instance if there is a tool that helps only in basic drawing but is really user friendly so that a beginner can draw electronics circuit diagram, then I would consider adding that particular software. Circuit drawing or electronic schematic drawing is not a hard to learn stuff, you can make it better with practice. Well there are some standard practices that you have to keep in mind while you draw. We will write an article regarding the standard practices to follow while drawing circuit diagrams.

Lets list out free circuit diagram drawing softwares first.

Free circuit drawing softwares list:-

PCB123 – This is a free circuit drawing software from Sunstone. You can do almost all your needs from design to build using PCB 123. PCB123 provides 500,000 parts with great search functionality to access all the parts while drawing. Datasheets of select parts are available. The interesting feature of this software is “real time” search for availability of parts from Digi-Key. Well, give it a try and give your opinions. After all it’s a free software from a reputed company like Sunstone.

Xcircuit is a free schematic drawing software from OpenCircuit designs, which is made for Unix/Linux environment. You can use this software on Windows if you have the X-server running or Windows API. This open source project is aimed at developing output schematics that are of high quality, ready for instant publication. Many versions of the software are available. You have to go through the tutorial thoroughly before you start using it.

TinyCad is a schematic drawing software for Windows from SourceForge. It supports circuit drawing, layout developing and circuit simulation. It is available for free download.

Dia Dia is a basic drawing software suitable for drawing block diagrams. They provide access to some basic and important components too. This software is only for a beginner or a new entrant in the electronics circuit drawing arena. I consider this software good for drawing block diagrams.Software has a GPL license and is made for Mac and Linux. I don’t know if they have a Windows version.

SmartDrawFree software for drawing electronics schematics. This software is from SmartDraw LLC which develops high end drawing softwares and CAD softwares. The free version is a tool for promoting their paid versions. So you may not expect great/advanced features in the free version.

Pspice – Student Version You all know about Pspice – the simulation software. Follow that link to get a free student version of the Pspice.

ProfiCAD is a free, basic tool for drawing. I haven’t used this yet, well try out and tell me.

Solve Elec is a free software for Windows and Mac.

Paid/Enterprise Softwares:

Tina – Tina is an affordable solution for small industries and freelancers. Facilitates circuit drawing, layout developments, simulation and other features. Real time testing of circuits is another notable feature.

Orcada highly popular software from Cadence for circuit drawing, layout development and simulation.

CadSoft Eagle – another high quality PCB design software. Easily Applicable Graphical Layout Editor is the abbreviation of EAGLE.

LTSpice is a simulation software from Linear. Schematic development, spice simulation, waveform viewer and many other features.

Altera – has a lot of softwares for your various needs. They have softwares for Embedded design (NIOS II), DSP design software (DSP Builder).  For logic design they have Quartus II and ModelSim.

PCB Pool – They don’t provide any softwares. This link is in fact a list of softwares for PCB design.

So I guess I have compiled a good enough list of circuit drawing softwares, which can be used for electronics circuit drawing, schematic layout drawing, wiring diagram drawing etc. I will add more softwares to this list if you can suggest it through our comments section.

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References for CMOS Analog Circuit Design

If you can review the references in the order well, then you’re on the right way…

1) Design of Analog CMOS Integrated Circuits, by Behzad Razavi

2) CMOS Analog Circuit Design, by Phillip E. Allen & Douglas R. Holberg

3) CMOS Circuit Design, Layout, and Simulation, by R. Jacob Baker

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